This invention relates to methods and circuits for dynamically adjusting a supply voltage and/or the frequency of a clock signal in a digital circuit wherein the power consumption in and/or processing capability of the digital circuit is optimised.
In portable digital devices, such as digital cellular telephones, and any other digital applications which are sensitive to power consumption or power dissipation, such as picocell cellular base stations, reducing power consumption is an important consideration. In portable devices powered by a battery for example, reducing power consumption can extend the period of time in which the portable device is operable, before the battery requires replacing or recharging. Even with non-battery powered devices, there is an advantage in reducing power dissipation in that it can improve reliability of the components of the device.
Digital circuits, which are part of a digital device, such as a digital cellular telephone, require as inputs a supply voltage Vdd and a clock signal. Power consumption (P) in such a digital circuit can be approximated by the following equation:
P=c*Fref*Vdd2
where
Fref is the frequency of the clock signal which clocks the digital circuit
c is the equivalent capacitance of the digital circuit
Vdd is the supply voltage of the digital circuit
Thus, from this equation it is clear that by reducing the clock frequency Fref and the supply voltage Vdd, but only to the limit that ensures proper function of the digital circuit, power consumption can be reduced.
A number of different methods for reducing power consumption have already been contemplated. For example, it is known for some applications to run the clock signal as fast as possible when processing is required and then when no processing is required, completely stopping the clock. This method could not be used in applications requiring some processing substantially all of the time. U.S. Pat. No. 5,378,935 discloses a method for optimising power consumption by adjusting the clock frequency of the clock signal according to the need for processing power. Both these methods achieve a linear decrease in power consumption.
Similarly it is also known to achieve a reduction in power consumption by running at a constant lower supply voltage. Since power consumption depends on Vdd2, such a reduction in the supply voltage achieves increased power savings. However, this may result in poorer performance which may be unacceptable in some applications.
Some known systems reduce power consumption by having a power down mode during which the supply voltage is zero. As with those systems which have periods in which the clock is completely stopped, this technique cannot be used in applications requiring some processing substantially all the time.
European Patent Application EP-A-0632360 describes a method for reducing power consumption by adjusting the frequency of the clock signal and the supply voltage according to the task to be performed. Like all the known methods, the method disclosed in this patent application does not take account of variations in circuit parameters with time and from circuit to circuit, due to for example, temperature, ageing and circuit fabrication process.
There is therefore a need for an improved method for dynamically controlling the power consumption in a digital circuit which overcomes the above referenced disadvantages.
In accordance with a first aspect of the present invention there is provided a method for dynamically adjusting a supply voltage in a digital circuit, the method comprising the steps of:
determining a propagation delay of a signal along a signal path in the digital circuit;
adjusting the level of the supply voltage in dependence on the determined propagation delay until the propagation delay is determined to reach a predetermined period, the supply voltage having a first level when the determined propagation delay reaches the predetermined period; and
providing the supply voltage having the first level to components of the digital circuit.
It will be appreciated that by adjusting the level of the supply voltage until the propagation delay reaches a predetermined period, which predetermined period preferably corresponds to the clock period of the clock signal which is clocking the gates of the path, the present invention can determine and use the optimum supply voltage for the path in real time. Thus, power consumption can be optimised in real time taking account of variations in circuit parameters with time and from circuit to circuit, due to for example, temperature, ageing and circuit fabrication process.
In a preferred arrangement, the signal is clocked along the signal path by a clock signal and the determining step comprises the steps of:
providing a duplicate path to the signal path, which duplicate path comprises substantially the same components as the signal path and has an input and an output;
applying the clock signal to the input of the duplicate path;
comparing the phase of the dock signal at the output of the duplicate path with the phase of the clock signal at the input of the duplicate path to provide a phase error signal, the phase error signal being zero when the propagation delay reaches the predetermined period, and
wherein the adjusting step comprises the step of adjusting the level of the supply voltage according to the phase error signal.
In accordance with a second embodiment of the first aspect of the invention, there is provided a method for dynamically adjusting a supply voltage in a digital circuit as recited in claim 7 in the following claims.
In accordance with a second aspect of the present invention there is provided a method for dynamically adjusting the frequency of a clock signal and supply voltage in the digital circuit, the method comprising the steps of:
determining a task to be performed by the digital circuit;
adjusting the frequency of the clock signal in dependence on the determined task and supplying the adjusted clock signal to components of the digital circuit;
determining a propagation delay of a signal along a signal path in the digital circuit;
adjusting the level of the supply voltage to provide an adjusted supply voltage in dependence on the adjusted frequency of the clock signal and on the determined propagation delay until the determined propagation delay reaches a predetermined period, the supply voltage having a first level when the determined propagation delay reaches the predetermined period; and
providing the supply voltage having the first level to components of the digital circuit.
In accordance with a third aspect of the invention there is provided a method for dynamically adjusting the clock frequency of a clock signal in a digital circuit, the method comprising the steps of:
generating and providing to components of the digital circuit a supply voltage having a predetermined level;
determining a propagation delay of a signal along a signal path in the digital circuit;
adjusting the clock frequency of the clock signal in dependence on the determined propagation delay until the propagation delay is determined to reach a predetermined period, the adjusted clock frequency having a first frequency when the determined propagation delay reaches the predetermined period; and
providing a clock signal having the first frequency to components of the digital circuit.
An advantage of this third aspect of the invention is that it enables the processing capability of a digital circuit to be increased according to the given conditions e.g. temperature.
In a preferred arrangement, a supply voltage having a maximum level is provided. When the propagation delay reaches the predetermined period the clock signal is at its maximum frequency for the digital circuit.